Advancements in the field of semiconductor processing have resulted in the development of micro-machining and micro-electromechanics. More specifically, micro-electromechanical systems (MEMS) have been fabricated using semiconductor processing techniques to form electrical and mechanical structures using a given substrate.
For example, some micro-electromechanical systems devices include cantilevers or other microstages of silicon which may be configured to be electrostatically actuated for various applications. Such MEMS devices may be used in exemplary applications including gyroscopes, accelerometers, tunable RF capacitors, digital mirrors, etc.
Exemplary MEMS devices including cantilever structures are described in Zhang and MacDonald, A RIE Process For Submicron, Silicon Electromechanical Structures, Cornell University (IOP Publishing Ltd. 1992), the teachings of which are incorporated herein by reference. A process is proposed in this publication for the formation of silicon cantilever beams with aluminum side electrodes for use as capacitor actuators. This prior art method is depicted herein as FIGS. 1-11.
Referring initially to FIG. 1, a silicon substrate 10, a silicon dioxide (SiO2) layer 12, and photoresist 14 are depicted. Layer 12 is formed to a thickness of 150 nm and photoresist 14 is patterned as illustrated.
Referring to FIG. 2, a mask defined by photoresist 14 shown in FIG. 1 is utilized to pattern silicon dioxide layer 12.
Referring to FIG. 3, plural trenches 16 are formed in substrate 10 utilizing reactive ion etching (RIE) according to the prior art process.
Referring to FIG. 4, thermal oxidation next occurs resulting in insulative layer 12a covering sidewalls and lower surfaces of trenches.
Referring to FIG. 5, contact windows 20 are opened over a surface of substrate 10 to enable desired electrical connection through insulative silicon dioxide layer 12a to substrate 10.
Referring to FIG. 6, an aluminum layer 22 is formed by physical vapor deposition (PVD) to a thickness of 400 nm. The sputtered aluminum layer 22 forms side electrodes 23 within trenches 16.
Referring to FIG. 7, photoresist 24 is formed upon the structure of FIG. 6 and is patterned to cover portions of aluminum layer 22 including side electrodes 23.
Referring to FIG. 8, portions of the aluminum layer 22 upon the bottom surfaces of trenches 16 are patterned as shown using photoresist 24.
Referring to FIG. 9, portions of silicon dioxide layer 12 within the bottoms of trenches 16 are patterned following patterning of aluminum layer 22.
Referring to FIG. 10, photoresist 24 of FIG. 9 is stripped from the structure.
Referring to FIG. 11, a cantilever 26 is released by isotropically etching silicon substrate 10 utilizing a fluorinated plasma (i.e., SiF6). Further details regarding the depicted prior art process are also described in U.S. Pat. No. 5,198,390, the teachings of which are incorporated herein by reference.
Modifications to this aforementioned process have been proposed by M. T. A. Saif and Noel C. MacDonald, as described herein.
In this modified process, the silicon release step described above with respect to FIG. 11 is performed prior to aluminum metallization. More specifically, the silicon is etched similar to FIG. 3 and plasma enhanced chemical vapor deposition PECVD or tetraethylorthosilicate (TEOS) deposition thereafter occurs. The resultant oxide is patterned, the silicon release etch is performed, and aluminum is deposited. This described process eliminates the need to pattern the metal or open contact holes.
The conventional described processes have associated drawbacks. Initially, the reactive ion etching of silicon substrate 10 shown in FIG. 3 typically results in a rough or scalloped etch profile. The roughness is duplicated in subsequent oxide and aluminum layers formed upon the sidewalls of trenches 16. Such roughness or scalloping compromises the functionality of the resultant device inasmuch as the area of the electrodes or capacitor plates is not well controlled. Further, such roughness or scalloping limits the scalability of the structure.
Also, the single crystal reactive etching and metallization process of the prior art contains multiple oxide and aluminum deposition and etch steps resulting in increased complexity.
In addition, the utilization of SF6 plasma to release the silicon cantilever 26 attacks the aluminum side electrodes 23. Although the aluminum is attacked weakly by this chemistry, such may lead to further undesirable non-uniformity of electrodes 23.
Accordingly, there exists a need to provide improved processing methodologies and structures which avoid the drawbacks associated with the prior art methodologies and devices.